Much research is currently being performed in the area of packing semiconductor devices and components into a single substrate. For example, much research and development has been performed in sub-micron or fine line photo-lithographic fabrication processes which enable the manufacture of very small semiconductor components.
As semiconductor devices and components are packed together with higher densities on a single substrate, it is often desirable to electrically isolate each component or groups of components from each other. One way to electrically isolate components is to form oxide isolation regions which serve to eliminate junction leakage between different isolated component groups. FIG. 1 illustrates a prior art LOCOS (local oxidation of silicon) process for forming an oxide isolation region. In a step (a), a thin SiO.sub.2 oxide layer 12 is grown on a silicon (Si) substrate 10. Then, a patterned Si.sub.3 N.sub.4 layer 14 is formed on the SiO.sub.2 layer 12. The Si.sub.3 N.sub.4 layer 14 is patterned (for example, using a photo-lithographic technique) to form Si.sub.3 N.sub.4 mesas 14a, 14b adjacent to an exposed window 16 of the SiO.sub.2 layer 12. The window 16 has the approximate desired dimensions, and is disposed in the approximate desired location of the oxide isolation region.
As shown in step (b), a channel stop 19 is formed in the substrate 10 surface below the window 16, for example, using an ion implantation technique. Then, in step (c), a field oxide 18 is formed in the substrate 10 surface below the window 16 by heating the substrate in an oxygen environment for a particular period of time. As shown, the field oxide isolation region thus formed has "bird's beak" shaped trailing edges 18a and 18b. In step (d), the Si.sub.3 N.sub.4 layer 14 is stripped from the substrate 10 and field oxide 18 surface. Then in step (e), sacrificial oxide growth and stripping are performed in order to overcome the "white ribbon effect".
The prior art LOGOS process of FIG. 1 has a number of disadvantages:
(1) Birds beaks 18a and 18b are formed in the field oxide 18 isolation region. The bird's beaks 18a and 18b are caused by lateral oxidation of the Si substrate 10 along the thin oxide layer 12 under the Si.sub.3 N.sub.4 layer 14 (which results from high temperature oxidation for a long time).
(2) A "white ribbon effect" is produced in the substrate 10 and SiO.sub.2 region 18 and layer 12. The white ribbon effect is caused by the diffusion of nitrogen from the compressive stressed Si.sub.3 N.sub.4 layer 14 into the adjacent tensile stressed Si substrate 10 and SiO.sub.2 field oxide isolation region 18 and oxide layer 12.
(3) The thickness of the field oxide 18 is thinned in the smaller openings 16a, 16b. This thinning effect is caused by a reduced oxygen gas flow into smaller sized LOCOS openings of the substrate 10 under the Si.sub.3 N.sub.4 mesas 14a and 14b.
(4) The field oxide isolation region 18 is not completely recessed within the substrate 10, but rather bows out and protrudes from the surface. This is due to the inherent increase in volume when the Si substrate 10 is oxidized to form SiO.sub.2. Furthermore, after the Si.sub.3 N.sub.4 layer 14 is stripped, there is a relaxation of stress inside the field oxide isolation region 18 edges. Thus, a "bird's head" and "bird's neck" shaped edge is always present.
(5) The conventional LOCOS process has a thermal budget with a long oxidation time (for forming the field oxide isolation region 18). Generally, the field oxide 18 thickness is proportional to the square root of the oxidation time in the conventional LOCOS process. Thus, a long oxidation time is required.
(6) Significant crystal lattice defects are introduced in the substrate 10 around the field oxide isolation region 18. These defects are caused by the tremendous stresses resulting from the pressure of the increased volume of the field oxide isolation region 18 on the surrounding substrate 10. Such defects make it impossible to eliminate junction leakage.
It is therefore the object of the present invention to overcome the disadvantages of the prior art.